Logic simulators have been used by designers to test the integrity of design without actually building the hardware. The logic simulator simulates the functions performed by the circuit and provides the designer an opportunity to examine the signals generated by the design. From these signals, the designer may uncover errors in the design.
In the event that a design error is found, the logic simulator allows the designer to modify the design and rerun the logic simulation, thereby decreasing the edit-debug cycle time and greatly reducing the overall circuit design time. Therefore, designers have come to rely on logic simulators as an essential design tool.
During the course of a logic simulation, certain signal values, such as those signals generated by the design, are stored for examination at the end of the simulation run. The availability of these signal values enable the user to determine whether errors have been uncovered by the simulation run. However, for simulations of more complex circuits that may run for hours or days, the number of signals that can be stored is greatly limited by the amount of available memory. Therefore, although the designer would like to examine most of the signal values to more accurately and expediently determine the errors, it may not be possible to specify all desirable signals. Consequently, the designer may be required to run a simulation multiple times to obtain all necessary information to diagnose the logic design error.
Once the designer has determined the problem and modified the design to eliminate the uncovered error, more simulation runs are required to ascertain the correctness of the correction and of the remainder of the design. It is likely more errors will be uncovered and corrected, and more simulations are run to further determine the accuracy of the design.
It is obvious from the foregoing that although logic simulators are invaluable design aides, they are not without problems. For example, they do not provide a designer access to all signal values for the duration of simulation time due to the large number of signals and the unavailability of memory. Certainly, to add memory capacity large enough for all the signal values would be impractical and expensive.
Additionally, logic simulators require an entire simulation to be rerun after the design has been modified to determine the correctness of the fix. To rerun an entire simulation may require days and weeks. Both aforementioned problems add considerably to the edit-debug time a designer must spend to ensure the correctness of the design.
The present invention is directed to overcoming one or more of the problems as set forth above.